000 | 00286 a2200085 4500 | ||
---|---|---|---|
020 | _a9781546776345 | ||
100 |
_aStuart Sutherland _918495 |
||
245 | _aRTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design | ||
260 |
_bSutherland HDL _c2017 |
||
999 |
_c12701 _d12701 |