Hachtel, Gary D. <br/><br/>
Logic synthesis and verification algorithms / 
by Gary Hachtel and Fabio Somenzi. 
 - New York :  Springer,  c2006. 
 - xxxii, 564 p. :  ill. ;  26 cm. 
<br/><br/>Includes bibliographical references and index. 
<br/><br/><label>ISBN: </label>9780387310046 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration--Design--Data processing.<br/>Logic design--Data processing.<br/>Integrated circuits--Verification.<br/>Computer-aided design.
<br/><br/><label>Dewey Class. No.: </label>621.395  / HAC/L