RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design (Record no. 12701)
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000 -LEADER | |
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fixed length control field | 00286 a2200085 4500 |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 9781546776345 |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Stuart Sutherland |
9 (RLIN) | 18495 |
245 ## - TITLE STATEMENT | |
Title | RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Name of publisher, distributor, etc. | Sutherland HDL |
Date of publication, distribution, etc. | 2017 |
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