Design through Verilog HDL / (Record no. 10274)
[ view plain ]
000 -LEADER | |
---|---|
fixed length control field | 00652nam a22002177a 4500 |
001 - CONTROL NUMBER | |
control field | TB9386 |
003 - CONTROL NUMBER IDENTIFIER | |
control field | IN-BhIIT |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20230728133558.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 200125b ||||| |||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9788126519316 |
040 ## - CATALOGING SOURCE | |
Original cataloging agency | IN-BhIIT |
041 ## - LANGUAGE CODE | |
Language code of text | eng |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 621.392 |
Book number | PAD/T |
100 1# - MAIN ENTRY--AUTHOR NAME | |
Personal name | Padmanabhan, T. R. |
Relator term | aurhor |
245 10 - TITLE STATEMENT | |
Title | Design through Verilog HDL / |
Statement of responsibility, etc | T. R. Padmanabhan and B. Bala Tripura Sundari |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication | New Delhi : |
Name of publisher | Wiley, |
Year of publication | c2004. |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | xii, 455p. ; |
Dimensions(size) | 24 cm. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Electrical and Electronics Engineering |
-- | VHDL |
700 ## - ADDED ENTRY--PERSONAL NAME | |
Personal name | Bala Tripura Sundari, B. |
Relator term | author |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | Text Book |
Koha issues (borrowed), all copies | 2 |
Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Date acquired | Full call number | Accession Number | Price effective from | Koha item type |
---|---|---|---|---|---|---|---|---|---|---|
Not withdrawn | Not Lost | not damaged | Central Library, IIT Bhubaneswar | Central Library, IIT Bhubaneswar | 25/01/2020 | 621.392 PAD/T | TB9386 | 25/01/2020 | Text Book |