Logic synthesis and verification algorithms /

Hachtel, Gary D.

Logic synthesis and verification algorithms / by Gary Hachtel and Fabio Somenzi. - New York : Springer, c2006. - xxxii, 564 p. : ill. ; 26 cm.

Includes bibliographical references and index.

9780387310046


Integrated circuits--Very large scale integration--Design--Data processing.
Logic design--Data processing.
Integrated circuits--Verification.
Computer-aided design.

621.395 / HAC/L

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